Senior RTL/SoC Functional Safety Engineer

About the role

Capgemini Engineering is seeking a Senior RTL/SoC Functional Safety Engineer to lead the development of complex ASIC and SoC solutions. You will focus on RTL design, functional safety compliance, and system‑level integration for safety‑critical hardware.

Key responsibilities

• Design and implement hardware functionality using Verilog/SystemVerilog.
• Develop and integrate functional safety mechanisms in compliance with ISO 26262.
• Translate safety requirements into RTL implementations and maintain traceability.
• Configure, integrate, and customize internal and third‑party IPs within complex SoC environments.
• Create and maintain IP‑level technical documentation, including safety assumptions and implementation details.
• Contribute to SoC architecture definition, subsystem design, and RTL micro‑architecture development.
• Collaborate with functional safety, verification, design, and system teams to ensure successful safety implementation.
• Support fault analysis, safety reviews, and produce functional safety work products throughout the development lifecycle.
• Participate in silicon development from architecture through integration and product delivery.

Required profile

• Strong experience in ASIC and/or SoC development on complex semiconductor projects.
• Hands‑on expertise in RTL design using Verilog/SystemVerilog.
• Practical knowledge of SoC architecture, integration, and subsystem development.
• Experience applying functional safety principles and ISO 26262 in hardware development.
• Proven ability to implement, integrate, and document safety mechanisms at RTL and system level.

Required skills

• Verilog
• SystemVerilog
• ASIC design
• SoC integration
• IP configuration and customization
• ISO 26262 functional safety
• Hardware safety analysis