Senior Design Verification Engineer

About the role

Cisco's SiliconOne team in Serbia is looking for a Senior Design Verification Engineer. The team specialises in ASIC functional verification for Cisco Silicon One chips, high-performance networking chips used by major data centres worldwide. You will work on functional verification using SystemVerilog/UVM, from architectural discussions through emulation and simulation support, alongside global teams, design and block owners, chiplet and full-chip owners, and emulation, compiler and software teams.

Key responsibilities

• Implement the DV infrastructure for block, cluster and TOP-level environments
• Maintain existing DV environments and enhance them
• Ensure complete verification coverage through code implementation and review, and functional coverage
• Work closely with architects and designers to ensure verification completeness
• Support tests run with emulation
• Take part in tasks preparing for post-silicon validation

Required profile

• 5+ years of experience in digital logic design verification
• Advanced debug skills before silicon and in the lab

Required skills

• Advanced knowledge of SystemVerilog and UVM
• Preferred: scripting abilities
• Preferred: system integration knowledge (AMBA, PCIe, SPI, I2C, JTAG, CPU)
• Preferred: basic software knowledge (chop driver level) and basic design knowledge