Senior Physical Design Engineer

About the role

We are looking for a Senior Physical Design Engineer to lead full‑chip and block‑level physical design on advanced technology nodes (10nm and below). You will own the complete design flow from floorplanning to sign‑off, ensuring high‑performance, low‑power ASICs.

Key responsibilities

• Perform deep floorplanning, partitioning, budgeting, power‑mesh distribution and clock‑tree planning/analysis.
• Execute scan re‑ordering, placement, CTS, and place‑and‑route activities.
• Drive timing closure, including signal‑integrity analysis and ECO implementation.
• Conduct validation tasks such as formal verification, EM/IR, DRC, LVS, antenna and ERC checks.
• Develop and maintain scripts for clock‑skew analysis, critical‑path evaluation, and constraint management.
• Participate in low‑power solution development and multiple high‑complexity design cycles with minimal supervision.

Required profile

• 8+ years of RTL‑to‑GDSII experience on 10nm or smaller nodes.
• Designs with 500k–1M+ instances.
• Strong background in ASIC physical design and sign‑off tape‑out activities.
• Proven ability to work independently on complex projects.

Required skills

• Physical design tools from Synopsys and/or Cadence.
• Floorplanning, power planning, CTS, placement, routing, and timing closure.
• Timing analysis, STA, PTSI, and signal‑integrity closure.
• ECO generation and implementation.
• Formal verification, EM/IR, DRC, LVS, antenna, and ERC analysis.
• Perl, TCL, Python scripting and Makefile proficiency.

What we offer

• Competitive salary and benefits.
• Respect for work‑life balance and personal choices.
• Access to all necessary high‑performance design tools.
• Long‑term stability and responsible corporate approach.