Hardware Verification Engineer 2 - Azure Core

About the role

Microsoft is looking for a Hardware Verification Engineer 2 to join its Azure Core team, which develops the next generation of networking devices for Azure's cloud datacenters. The work sits within a hardware/software co-design approach that uses hardware to accelerate computations and functions of the Azure network, and involves working with large software teams on customer-facing applications.

Key responsibilities

• Own the verification of one or more features of a custom block or subsystem integration.
• Define and implement efficient UVM-based verification environments to verify digital designs deployed in Microsoft's cloud datacenters.
• Implement verification coverage metrics and drive them toward 100% coverage.
• Build and promote modern verification workflows, including AI-assisted techniques that improve environment development, automation, debug efficiency, coverage analysis and execution quality.
• Define verification plans, quality metrics, regression strategy and coverage goals aligned with project milestones.
• Work closely with architecture, design, system engineering and software partners to identify risks early, resolve complex issues and deliver high-quality silicon subsystems.

Required profile

• Master's degree in Electrical Engineering, Computer Engineering or a related field; or a Bachelor's degree in the same fields plus some technical engineering experience; or equivalent experience.
• Ability to meet Microsoft, customer and/or government security screening requirements, including the Microsoft Cloud Background Check, which must be passed on hire and every two years thereafter.

Required skills

• Proficiency in SystemVerilog-based verification environments and methodologies such as UVM, assertions, constrained-random verification and coverage-driven verification (preferred).
• Proven experience verifying digital designs (preferred).
• Ability to articulate end goals and trade-offs on ill-defined engineering challenges (preferred).
• Experience applying AI-assisted techniques to improve silicon design or verification productivity, debug, coverage, automation or workflow efficiency (preferred).