Staff Engineer – Digital Functional Verification

About the role

As a Staff Engineer in Digital Functional Verification you will ensure efficient development of Infineon products, delivering high‑quality designs with first‑time success. You will work closely with global development sites and contribute to the creation of robust verification environments.

Key responsibilities

• Maintain continuous contact with worldwide development sites and support verification projects.
• Share knowledge and best practices across Infineon’s business units.
• Collaborate with application engineering and other disciplines to define verification methodology and plans.
• Design and develop UVM‑based verification environments for ICs.
• Identify sub‑modules suitable for simulation or formal verification and apply the appropriate method.
• Implement test scenarios in SystemVerilog using a constrained‑random approach.
• Manage verification activities at module level, including planning, tracking and reporting.
• Use Unified Power Format (UPF) to verify low‑power aspects of designs.

Required profile

• Degree in Electrical Engineering, Computer Science or a related field.
• At least 5 years of experience in metric‑driven digital and mixed‑signal verification and formal verification.
• Strong problem‑solving skills, detail‑oriented and committed to high‑quality outcomes.
• Excellent communication abilities and experience working in cross‑functional, international teams.
• Fluency in English.

Required skills

• SystemVerilog
• Universal Verification Methodology (UVM)
• Unified Power Format (UPF)
• Formal verification techniques
• Metric‑driven verification
• Mixed‑signal verification
• RTL design (SystemVerilog/VHDL)
• Ethernet protocol knowledge (bridge, PHY, MAC)
• Cadence verification tools (optional)
• SVAs, PSL (optional)