Senior Design Verification Engineer
Cisco · Belgrade
Description du poste
About the role
Join Cisco's SiliconOne team in Serbia, focusing on ASIC functional verification for high‑performance networking chips used in data centers worldwide. You will work on SystemVerilog/UVM verification, collaborating with global design, emulation, compiler and software teams.
Key responsibilities
- Implement DV infrastructure for block, cluster, and top‑level environments.
- Maintain and enhance existing verification environments.
- Ensure complete verification coverage through code and functional coverage implementation and review.
- Collaborate with architects and designers to guarantee verification completeness.
- Support emulation tests and prepare for post‑silicon validation.
Required profile
- 5+ years of experience in digital logic design verification.
- Advanced knowledge of SystemVerilog and UVM.
- Advanced debug skills pre‑silicon and in‑lab.
Required skills
- Scripting abilities.
- System integration knowledge (AMBA, PCIe, SPI, I2C, JTAG, CPU).
- Basic software knowledge at chip‑driver level.
- Basic design knowledge.
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Belgrade
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