Senior Design Verification Engineer (Hybrid – Belgrade/Bucharest)

About the role

We are looking for a Senior Design Verification Engineer to join our team and focus on verification of advanced interconnect systems in state‑of‑the‑art microprocessors. The position is based in Belgrade, Serbia (priority) or Bucharest, Romania with a hybrid work format.

Key responsibilities

• Perform pre‑silicon verification of next‑generation high‑performance microprocessor designs and related IPs.
• Develop, document and execute verification test plans at the unit level of the design hierarchy.
• Create high‑level testbench components (stimulus drivers, behavioral models, monitors, checkers) in SystemVerilog.
• Simulate and debug directed and random stimulus to ensure design functionality meets specifications.

Required profile

• 5+ years of experience in digital design verification.
• Strong proficiency with SystemVerilog and UVM.
• Good skills in Verilog.
• Experience maintaining existing verification environments and building new ones from scratch.
• Hands‑on experience with functional verification tools such as VCS, Cadence, and Mentor Graphics.
• Proficiency in Unix/Linux environments and scripting (Perl, Shell, Ruby).
• English language level B2 or higher.

Required skills

• SystemVerilog
• UVM
• Verilog
• VCS
• Cadence
• Mentor Graphics
• Unix/Linux
• Perl
• Shell
• Ruby